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Micrel, Inc.
(/1, /2, /4) OR (/2, /4, /8) CLOCK GENERATION CHIP
Precision Edge(R) Precision SY100S834 Edge(R) SY100S834L
SY100S834 SY100S834L
FEATURES
s s s s s s 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 16-pin SOIC package Precision Edge(R)
DESCRIPTION
The SY100S834/L is low skew (/1, /2, /4) or (/2, /4, /8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system.
TRUTH TABLE
CLK Z ZZ X EN L H X MR L L H Function Divide Hold Q0-2 Reset Q0-2
Notes: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition
FSEL L H
Q0 Outputs Divide by 2 Divide by 1
Q1 Outputs Divide by 4 Divide by 2
Q2 Outputs Divide by 8 Divide by 4
PIN NAMES
Pin CLK FSEL EN MR VBB Q0 Q1 Q2 Function Differential Clock Inputs Function Select Synchronous Enable Master Reset Reference Output Differential /1 or /2 Outputs Differential /2 or /4 Outputs Differential /4 or /8 Outputs
Precision Edge is a registered trademark of Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690
Rev.: G Amendment: /0
1
Issue Date: March 2006
Micrel, Inc.
Precision Edge(R) SY100S834 SY100S834L
PACKAGE/ORDERING INFORMATION
Ordering Information
Q0 1 Q0
2
Q
/1 or /2
16 VCC
R
Part Number SY100S834ZC SY100S834ZCTR(1) SY100S834LZC SY100S834LZCTR(1) SY100S834ZI SY100S834ZITR(1) SY100S834LZI SY100S834LZITR(1) SY100S834ZG(2) SY100S834ZGTR(1, 2) SY100S834LZG(2)
Package Type Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2 Z16-2
Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Package Marking SY100S834ZC SY100S834ZC SY100S834LZC SY100S834LZC SY100S834ZI SY100S834ZI SY100S834LZI SY100S834LZI
Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb Sn-Pb Sn-Pb Sn-Pb Sn-Pb
15
Q D R
EN
VCC 3 Q1 4
Q
14
FSEL
13 CLK
/2 or /4
Q1 5 VCC 6 Q2 Q2
7
R
12 CLK 11 VBB 10
MR VEE
Q
8
/4 or /8
R
9
SY100S834ZG with NiPdAu Pb-Free bar-line indicator Pb-Free SY100S834ZG with NiPdAu Pb-Free bar-line indicator Pb-Free SY100S834LZG with NiPdAu Pb-Free bar-line indicator Pb-Free SY100S834LZG with NiPdAu Pb-Free bar-line indicator Pb-Free
16-Pin SOIC (Z16-2)
SY100S834LZGTR(1, 2)
Notes: 1. Tape and Reel. 2. Pb-Free package is recommended for new designs.
M9999-032206 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY100S834 SY100S834L
DC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol IEE VBB IIH Parameter Power Supply Current Min. -- Typ. -- -- -- Max. 49 -1.26 150 Min. -- -1.38 -- TA = 0C Typ. -- -- -- Max. 49 -1.26 150 TA = +25C Min. -- -1.38 -- Typ. -- -- -- Max. 49 TA = +85C Min. -- Typ. -- -- -- Max. 54 -1.26 150 Unit mA V A
Output Reference Voltage -1.38 Input HIGH Current --
-1.26 -1.38 150 --
Note: 1. Parametric values specified at:
5 volt Power Supply Range 3 volt Power Supply Range
100S834 Series: 100S834L Series
-4.2V to -5.5V. -3.0V to -3.8V.
AC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol tPLH tPHL tskew tS tH VPP VCMR tr tf Parameter Propagation Delay to Output CLK MR Min. 960 650 -- 400 200 250 -1.3 275 Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 Min. 960 650 -- 400 200 250 -1.4 275 TA = 0C Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 TA = +25C Min. 960 650 -- 400 200 250 -1.4 275 Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 TA = +85C Min. 960 650 -- 400 200 250 -1.4 275 Typ. Max. Unit ps ps ps ps mV V ps
1100 1200 800 1010 -- -- -- -- -- 400 50 -- -- -- -0.4 525
Within-Device Skew(2) Set-up Time EN Hold Time EN Minimum Input Swing Common Mode Range(3) CLK Output Rise/Fall Times Q (20% - 80%)
Notes: 1. Parametric values specified at:
5 volt Power Supply Range 100S834 Series: -4.2V to -5.5V. 3 volt Power Supply Range 100S834L Series -3.0V to -3.8V. 2. Within-Device Skew is specified for identical transition. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V - IVCMR (min)I.
M9999-032206 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY100S834 SY100S834L
TIMING DIAGRAM
Internal Clock Disabled CLK FSEL = 0 Q0 Q1 Q2 FSEL = 1 Q0 Q1 Q2 EN
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
M9999-032206 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY100S834 SY100S834L
16-PIN SOIC .150" WIDE (Z16-2)
Rev. 02
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-032206 hbwhelp@micrel.com or (408) 955-1690
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